BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Chicago
X-LIC-LOCATION:America/Chicago
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20181221T160908Z
LOCATION:D221
DTSTART;TZID=America/Chicago:20181113T153000
DTEND;TZID=America/Chicago:20181113T164500
UID:submissions.supercomputing.org_SC18_sess279@linklings.com
SUMMARY:Doctoral Showcase III
DESCRIPTION:Doctoral Showcase\nArchitectures, Memory, Runtime Systems, Sto
 rage, Workshop Reg Pass, Tutorial Reg Pass, Tech Program Reg Pass, Exhibit
 s Reg Pass, Exhibits - Exhibit Hall Only Reg Pass, Doctoral Showcase\n\nDe
 signing High-Performance, Resilient, and Heterogeneity-Aware Key-Value Sto
 rage for Modern HPC Clusters\n\nShankar, Panda, Lu\n\nDistributed key-valu
 e stores are being increasingly used to accelerate Big Data workloads on m
 odern HPC clusters. The advances in HPC technologies (e.g., RDMA, SSDs) ha
 s directed several efforts towards employing hybrid storage with RDMA, for
  designing high- performance key-value stores. With this a...\n\n---------
 ------------\nHardware Transactional Persistent Memory\n\nGiles, Varman\n\
 nThis research solves the problem of creating durable transactions in byte
 -addressable Non-Volatile Memory or Persistent Memory (PM) when using Hard
 ware Transactional Memory (HTM)-based concurrency control.  It shows 
 how HTM transactions can be ordered correctly and atomically into PM by th
 e use...\n\n---------------------\nThe Algorithm and Framework Designs and
  Optimizations for Scalable Automata Processing on HPC Platforms\n\nYu, Ya
 o\n\nAutomata processing could perform as the core of many applications in
  the areas such as network security, text mining, and bioinformatics. Achi
 eving high-speed and scalable automata processing is exceptionally challen
 ging. For one thing, the classic DFA representation is memory-bandwidth ef
 ficient b...\n\n---------------------\nEfficient Deployment of Irregular C
 omputations on Multi- and Many-Core Architectures\n\nWu, Becchi\n\nMulti- 
 and manycore processors have been advancing High Performance Computing wit
 h their high throughput and power efficiency. There has been an increasing
  interest in accelerating irregular computations on these devices that off
 er massive parallelism. My thesis focuses on compiler techniques and co...
 \n\n---------------------\nHigh Performance Middlewares for Next Generatio
 n Architectures: Challenges and Solutions\n\nChakraborty, Panda\n\nThe eme
 rgence of modern multi-/many-core architectures and high-performance inter
 connects have fueled the growth of large-scale supercomputing clusters. Du
 e to this unprecedented growth in scale and compute density, high performa
 nce computing (HPC) middlewares now face a plethora of new challenges t...
 \n
END:VEVENT
END:VCALENDAR