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DTSTAMP:20181221T160742Z
LOCATION:D221
DTSTART;TZID=America/Chicago:20181113T154500
DTEND;TZID=America/Chicago:20181113T160000
UID:submissions.supercomputing.org_SC18_sess279_drs124@linklings.com
SUMMARY:High Performance Middlewares for Next Generation Architectures: Ch
 allenges and Solutions
DESCRIPTION:Doctoral Showcase\nArchitectures, Memory, Runtime Systems, Sto
 rage, Workshop Reg Pass, Tutorial Reg Pass, Tech Program Reg Pass, Exhibit
 s Reg Pass, Exhibits - Exhibit Hall Only Reg Pass, Doctoral Showcase\n\nHi
 gh Performance Middlewares for Next Generation Architectures: Challenges a
 nd Solutions\n\nChakraborty, Panda\n\nThe emergence of modern multi-/many-
 core architectures and high-performance interconnects have fueled the grow
 th of large-scale supercomputing clusters. Due to this unprecedented growt
 h in scale and compute density, high performance computing (HPC) middlewar
 es now face a plethora of new challenges to solve in order to extract the 
 best performance from such systems. In this work, we study four such chall
 enges - a) launching and bootstrapping jobs on very large scale clusters, 
 b) contention in collective communication, c) point-to-point communication
  protocols, and d) scalable fault-tolerance and recovery and propose effic
 ient solutions for them. The proposed solutions have been implemented on M
 VAPICH2, a popular MPI and PGAS runtime used by scientists and HPC cluster
 s around the world.
URL:https://sc18.supercomputing.org/presentation/?id=drs124&sess=sess279
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