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DTSTAMP:20181221T160742Z
LOCATION:D221
DTSTART;TZID=America/Chicago:20181113T163000
DTEND;TZID=America/Chicago:20181113T164500
UID:submissions.supercomputing.org_SC18_sess279_drs126@linklings.com
SUMMARY:Efficient Deployment of Irregular Computations on Multi- and Many-
 Core Architectures
DESCRIPTION:Doctoral Showcase\nArchitectures, Memory, Runtime Systems, Sto
 rage, Workshop Reg Pass, Tutorial Reg Pass, Tech Program Reg Pass, Exhibit
 s Reg Pass, Exhibits - Exhibit Hall Only Reg Pass, Doctoral Showcase\n\nEf
 ficient Deployment of Irregular Computations on Multi- and Many-Core Archi
 tectures\n\nWu, Becchi\n\nMulti- and manycore processors have been advanci
 ng High Performance Computing with their high throughput and power efficie
 ncy. There has been an increasing interest in accelerating irregular compu
 tations on these devices that offer massive parallelism. My thesis focuses
  on compiler techniques and code transformations that facilitate the deplo
 yment of irregular computations on multi- and many-core processors, aiming
  to achieve higher performance and better programmability.  My contri
 butions are below. We propose a compiler-based consolidation framework to 
 improve the efficiency of irregular graph and tree computations written wi
 th Dynamic Parallelism on GPUs. We analyze and categorize parallel recursi
 ve tree traversal patterns, then provide insights on how to select the pla
 tform and code template based on identified traversal patterns. We propose
  compiler techniques to support a SIMT programming model on Intel multi- a
 nd many-core architectures with wide vector units, and point out the main 
 challenges in supporting the SIMT model, especially for irregular computat
 ions.
URL:https://sc18.supercomputing.org/presentation/?id=drs126&sess=sess279
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