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DTSTAMP:20181221T160904Z
LOCATION:C2/3/4 Ballroom
DTSTART;TZID=America/Chicago:20181113T083000
DTEND;TZID=America/Chicago:20181113T170000
UID:submissions.supercomputing.org_SC18_sess325_spost118@linklings.com
SUMMARY:Mitigating Performance and Progress Variability in Iterative Async
 hronous Algorithms
DESCRIPTION:ACM Student Research Competition, Poster\nTech Program Reg Pas
 s, Exhibits Reg Pass\n\nMitigating Performance and Progress Variability in
  Iterative Asynchronous Algorithms\n\nZarins\n\nLarge HPC machines are sus
 ceptible to irregular performance. Factors like chip manufacturing differe
 nces, heat management, and network congestion combine to result in varying
  execution time for the same code and input sets. Asynchronous algorithms 
 offer a partial solution. In these algorithms, fast workers are not forced
  to synchronize with slow ones. Instead they continue computing updates, a
 nd moving toward the solution, using the latest data available to them, wh
 ich may have become stale (i.e. a number of iterations out of date compare
 d to the most recent data). While this allows for high computational effic
 iency, the convergence rate of asynchronous algorithms tends to be lower.\
 n\nTo address this problem, we are using the unique properties of asynchro
 nous algorithms to develop load balancing strategies for iterative asynchr
 onous algorithms in both shared and distributed memory. Our poster shows h
 ow our solution attenuates noise, resulting in significant reduction progr
 ess imbalance and time-to-solution variability.
URL:https://sc18.supercomputing.org/presentation/?id=spost118&sess=sess325
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