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DTSTAMP:20181221T160904Z
LOCATION:C2/3/4 Ballroom
DTSTART;TZID=America/Chicago:20181113T083000
DTEND;TZID=America/Chicago:20181113T170000
UID:submissions.supercomputing.org_SC18_sess325_spost136@linklings.com
SUMMARY:Hardware Transactional Persistent Memory
DESCRIPTION:ACM Student Research Competition, Poster\nTech Program Reg Pas
 s, Exhibits Reg Pass\n\nHardware Transactional Persistent Memory\n\nGiles\
 n\nThis research solves the problem of creating durable transactions in by
 te-addressable Non-Volatile Memory or Persistent Memory (PM) when using Ha
 rdware Transactional Memory (HTM)-based concurrency control.  It shows how
  HTM transactions can be ordered correctly and atomically into PM by the u
 se of a novel software protocol.  We exploit the ordering mechanism to des
 ign a novel persistence method that decouples HTM concurrency from back-en
 d PM operations.  Failure atomicity is achieved using redo logging coupled
  with aliasing to guard against mistimed cache evictions.\n\nThe algorithm
  uses efficient lock-free mechanisms with bounded static memory requiremen
 ts and executes on existing Intel based processors.  A back-end distribute
 d memory controller alternative provides a hardware implementation choice 
 for catching PM cache evictions.  Our approach compares well with standard
  (volatile) HTM transactions and yields significant gains in latency and t
 hroughput over other persistence methods.
URL:https://sc18.supercomputing.org/presentation/?id=spost136&sess=sess325
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