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BEGIN:VEVENT
DTSTAMP:20181221T160742Z
LOCATION:C2/3/4 Ballroom
DTSTART;TZID=America/Chicago:20181113T171500
DTEND;TZID=America/Chicago:20181113T190000
UID:submissions.supercomputing.org_SC18_sess343_drs118@linklings.com
SUMMARY:Hardware Transactional Persistent Memory
DESCRIPTION:Doctoral Showcase\nWorkshop Reg Pass, Tutorial Reg Pass, Tech 
 Program Reg Pass, Exhibits Reg Pass, Exhibits - Exhibit Hall Only Reg Pass
 \n\nHardware Transactional Persistent Memory\n\nGiles, Varman\n\nThis rese
 arch solves the problem of creating durable transactions in byte-addressab
 le Non-Volatile Memory or Persistent Memory (PM) when using Hardware Trans
 actional Memory (HTM)-based concurrency control.  It shows how HTM tr
 ansactions can be ordered correctly and atomically into PM by the use of a
  novel software protocol.  We exploit the ordering mechanism to desig
 n a novel persistence method that decouples HTM concurrency from back-end 
 PM operations.  Failure atomicity is achieved using redo logging coup
 led with aliasing to guard against mistimed cache evictions.<br /><br />Th
 e algorithm uses efficient lock-free mechanisms with bounded static memory
  requirements and executes on existing Intel based processors.  A bac
 k-end distributed memory controller alternative provides a hardware implem
 entation choice for catching PM cache evictions.  Our approach compar
 es well with standard (volatile) HTM transactions and yields significant g
 ains in latency and throughput over other persistence methods.
URL:https://sc18.supercomputing.org/presentation/?id=drs118&sess=sess343
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