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DTSTAMP:20181221T160742Z
LOCATION:C2/3/4 Ballroom
DTSTART;TZID=America/Chicago:20181113T171500
DTEND;TZID=America/Chicago:20181113T190000
UID:submissions.supercomputing.org_SC18_sess343_drs126@linklings.com
SUMMARY:Efficient Deployment of Irregular Computations on Multi- and Many-
 Core Architectures
DESCRIPTION:Doctoral Showcase\nWorkshop Reg Pass, Tutorial Reg Pass, Tech 
 Program Reg Pass, Exhibits Reg Pass, Exhibits - Exhibit Hall Only Reg Pass
 \n\nEfficient Deployment of Irregular Computations on Multi- and Many-Core
  Architectures\n\nWu, Becchi\n\nMulti- and manycore processors have been a
 dvancing High Performance Computing with their high throughput and power e
 fficiency. There has been an increasing interest in accelerating irregular
  computations on these devices that offer massive parallelism. My thesis f
 ocuses on compiler techniques and code transformations that facilitate the
  deployment of irregular computations on multi- and many-core processors, 
 aiming to achieve higher performance and better programmability.  My 
 contributions are below. We propose a compiler-based consolidation framewo
 rk to improve the efficiency of irregular graph and tree computations writ
 ten with Dynamic Parallelism on GPUs. We analyze and categorize parallel r
 ecursive tree traversal patterns, then provide insights on how to select t
 he platform and code template based on identified traversal patterns. We p
 ropose compiler techniques to support a SIMT programming model on Intel mu
 lti- and many-core architectures with wide vector units, and point out the
  main challenges in supporting the SIMT model, especially for irregular co
 mputations.
URL:https://sc18.supercomputing.org/presentation/?id=drs126&sess=sess343
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