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BEGIN:VEVENT
DTSTAMP:20181221T160744Z
LOCATION:Booth 619
DTSTART;TZID=America/Chicago:20181115T100000
DTEND;TZID=America/Chicago:20181115T150000
UID:submissions.supercomputing.org_SC18_sess500_emt103@linklings.com
SUMMARY:Parallelware Analyzer: Speeding Up the Parallel Software Developme
 nt Lifecycle.
DESCRIPTION:Emerging Technologies\nTech Program Reg Pass, Exhibits Reg Pas
 s, Exhibits - Exhibit Hall Only Reg Pass\n\nParallelware Analyzer: Speedin
 g Up the Parallel Software Development Lifecycle.\n\nCollis, Arenaz, Novo 
 Rodríguez, Otero Oubiña, González Cuevas...\n\nParallelware Analyzer is th
 e second product in the Parallelware Tools Suite and is being designed aro
 und the needs of the user.  Parallelware Analyzer is a command line report
 ing tool designed to help the HPC application developer speed up their dev
 elopment process, and also provide the HPC service provider a detailed und
 erstanding of what parallelization software solutions are being used on th
 eir systems. The tool enables the user to ‘zoom in’ on what they need to k
 now, providing key information for understanding hybrid MPI+X applications
  from the point of view of computations, memory and control flow. The repo
 rts will cover code features such as understanding memory access patterns,
  data layout and data scoping; identifying functions free of side-effects 
 beyond procedure boundaries; analyzing dependencies beyond loop boundaries
  to identify regions that are already parallelized and computational patte
 rns that offer parallelization opportunities; annotating the source code w
 ith parallelization primitives including vectorization, SIMD, multi-thread
 ing, offloading to accelerators etc. This is all done by static analysis o
 f the source code using LLVM-based compiler technology, without the need t
 o ‘instrument’ or benchmark your code and can even be run on your laptop, 
 irrespective of how many cores your code is designed to run on.
URL:https://sc18.supercomputing.org/presentation/?id=emt103&sess=sess500
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