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DTSTAMP:20181221T160744Z
LOCATION:Booth 619
DTSTART;TZID=America/Chicago:20181115T100000
DTEND;TZID=America/Chicago:20181115T150000
UID:submissions.supercomputing.org_SC18_sess500_emt107@linklings.com
SUMMARY:The Data-Centric Future and Gen-Z's Next Generation Interconnect
DESCRIPTION:Emerging Technologies\nTech Program Reg Pass, Exhibits Reg Pas
 s, Exhibits - Exhibit Hall Only Reg Pass\n\nThe Data-Centric Future and Ge
 n-Z's Next Generation Interconnect\n\nBowman\n\nCurrent computer architect
 ures allow for network and storage transfers to occur at much lower rates 
 than memory transfers, so they must have separate buses, control signals, 
 and command structures. Processors must wait endlessly for these transfers
  to finish or must find other work to do. A great deal of time is spent mo
 ving data between buffers to allow components working at highly different 
 speeds to communicate effectively. Extra hardware is often needed to creat
 e DMA channels that perform transfers outside the normal flow of instructi
 ons and data. Resuming or cancelling partially completed transfers is diff
 icult and error-prone. Gen-Z technology is different: a high-bandwidth, lo
 w-latency fabric with separate media and memory controllers that can be re
 alized inside or beyond traditional chassis limits. Gen-Z enables much hig
 her throughput and much lower complexity for big data solutions in such ap
 plications as data analytics, deep packet inspection, artificial intellige
 nce, machine learning, and video and image processing.  \n\nThe Gen-Z Cons
 ortium, an industry consortium comprised of over 50 leading technology com
 panies, recently released its Core Specification 1.0 to the public.
URL:https://sc18.supercomputing.org/presentation/?id=emt107&sess=sess500
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