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DTSTART:19700308T020000
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DTSTAMP:20260522T150117Z
LOCATION:D171/173
DTSTART;TZID=America/Chicago:20181116T110000
DTEND;TZID=America/Chicago:20181116T111500
UID:submissions.supercomputing.org_SC18_sess145_ws_p3hpc111@linklings.com
SUMMARY:Delivering Performance-Portable Stencil Computations on CPUs and G
 PUs Using Bricks
DESCRIPTION:Tuowen Zhao (University of Utah), Samuel Williams (Lawrence Be
 rkeley National Laboratory), Mary Hall (University of Utah), and Hans Joha
 nsen (Lawrence Berkeley National Laboratory)\n\nAchieving high performance
  on stencil computations poses a number of challenges on modern architectu
 res. The optimization strategy varies significantly across architectures, 
 types of stencils, and types of applications. The standard approach to ada
 pting stencil computations to different architectures, used by both compil
 ers and application programmers, is through the use of iteration space til
 ing, whereby the data footprint of the computation and its computation par
 titioning are adjusted to match the memory hierarchy and available paralle
 lism of different platforms.  In this paper, we explore an alternative per
 formance portability strategy for stencils, a data layout library for sten
 cils called bricks, that adapts data footprint and parallelism through fin
 e-grained data blocking. Bricks are designed to exploit the inherent multi
 -dimensional spatial locality of stencils, facilitating improved code gene
 ration that can adapt to CPUs or GPUs, and reducing pressure on the memory
  system.  We demonstrate that bricks are performance-portable across CPU a
 nd GPU architectures and afford performance advantages over various tiling
  strategies, particularly for modern multi-stencil and high-order stencil 
 computations. For a range of stencil computations, we achieve high perform
 ance on both the Intel Knights Landing (Xeon Phi) and Skylake (Xeon) CPUs 
 as well as the Nvidia P100 (Pascal) GPU delivering up to a 5x speedup agai
 nst tiled code.\n\nTag: Heterogeneous Systems, Performance\n\nRegistration
  Category: Workshop Reg Pass\n\nSession Chair: Rob Neely (Lawrence Livermo
 re National Laboratory)\n\n
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