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LOCATION:D165
DTSTART;TZID=America/Chicago:20181112T170000
DTEND;TZID=America/Chicago:20181112T173000
UID:submissions.supercomputing.org_SC18_sess161_ws_pmbsf122@linklings.com
SUMMARY:Automated Instruction Stream Throughput Prediction for Intel and A
 MD Microarchitectures
DESCRIPTION:Jan Laukemann (University of Erlangen-Nuremberg); Julian Hamme
 r (University of Erlangen-Nuremberg, Erlangen Regional Computing Center); 
 Johannes Hofmann (University of Erlangen-Nuremberg); Georg Hager (Universi
 ty of Erlangen-Nuremberg, Erlangen Regional Computing Center); and Gerhard
  Wellein (University of Erlangen-Nuremberg)\n\nAn accurate prediction of s
 cheduling and execution of instruction streams is a necessary prerequisite
  for predicting the in-core performance behavior of throughput-bound loop 
 kernels on out-of-order processor architectures. Such predictions are an i
 ndispensable component of analytical performance models, such as the Roofl
 ine and the Execution-Cache-Memory (ECM) model, and allow a deep understan
 ding of the performance-relevant interactions between hardware architectur
 e and loop code.\n\nWe present the Open Source Architecture Code Analyzer 
 (OSACA), a static analysis tool for predicting the execution time of seque
 ntial loops comprising x86 instructions under the assumption of an infinit
 e first-level cache and perfect out-of-order scheduling. We show the proce
 ss of building a machine model from available documentation and semi-autom
 atic benchmarking, and carry it out for the latest Intel Skylake and AMD Z
 en micro-architectures.\n\nTo validate the constructed models, we apply th
 em to several assembly kernels and compare runtime predictions with actual
  measurements. Finally we give an outlook on how the method may be general
 ized to new architectures.\n\nTag: Benchmarks, Parallel Programming Langua
 ges, Libraries, and Models, Performance, Simulation\n\nRegistration Catego
 ry: Workshop Reg Pass\n\nSession Chair: Steven A. Wright (University of Yo
 rk, England)\n\n
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