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DTSTART;TZID=America/Chicago:20181112T090000
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UID:submissions.supercomputing.org_SC18_sess168@linklings.com
SUMMARY:IA^3 2018: 8th Workshop on Irregular Applications: Architectures a
 nd Algorithms
DESCRIPTION:Workshop Lunch (on your own)\n---------------------\nA Block-O
 riented, Parallel, and Collective Approach to Sparse Indefinite Preconditi
 oning on GPUs\n\nLarge sparse symmetric indefinite matrices are notoriousl
 y hard to precondition. They often lack  diagonal dominance and exhibit Sc
 hur-complements that render zero fill-in factorization preconditioning ine
 ffective. Pivoting, a necessity for stable LDLt factorizations, complicate
 s parallel approaches...\n\n\nDaniel Thuerck (Technical University Darmsta
 dt); Maxim Naumov (Facebook); Michael Goesele (Graphics, Capture and Massi
 vely Parallel Computing; Technical University Darmstadt); and Michael Garl
 and (Nvidia Corporation)\n---------------------\nThere Are Trillions of Li
 ttle Forks in the Road:  Choose Wisely! -- Estimating the Cost and Likelih
 ood of Success of Constrained Walks to Optimize a Graph Pruning Pipeline\n
 \nWe have developed [Reza et al. SC18] a highly scalable algorithmic pipel
 ine for pattern matching in labeled graphs and demonstrated it on trillion
 -edge graphs. This pipeline: (i) supports arbitrary search patterns, (ii) 
 identifies all the vertices and edges that participate in matches - offeri
 ng 100...\n\n\nNicolas Tripoul, Hassan Halawa, and Tahsin Reza (University
  of British Columbia); Geoffrey Sanders and Roger Pearce (Lawrence Livermo
 re National Laboratory); and Matei Ripeanu (University of British Columbia
 )\n---------------------\nIA^3 Debate\n\nThe IA^3 oxfordian debate!\n\n\nJ
 ohn Feo (Pacific Northwest National Laboratory)\n---------------------\nSo
 ftware Prefetching for Unstructured Mesh Applications\n\nApplications that
  exhibit regular memory access patterns usually benefit transparently from
  hardware prefetchers that bring data into the fast on-chip cache just bef
 ore it is required, thereby avoiding expensive cache misses. In contrast, 
 unstructured mesh applications contain irregular access patte...\n\n\nIoan
  Hadade (Oxford Thermofluids Institute, University of Oxford); Timothy M. 
 Jones (University of Cambridge); and Feng Wang and Luca di Mare (Oxford Th
 ermofluids Institute, University of Oxford)\n---------------------\nWorksh
 op Afternoon Break\n---------------------\nImpact of Traditional Sparse Op
 timizations on a Migratory Thread Architecture\n\nAchieving high performan
 ce for sparse applications is challenging due to irregular access patterns
  and weak locality. These properties preclude many static optimizations an
 d degrade cache performance on traditional systems. To address these chall
 enges, novel systems such as the Emu architecture have...\n\n\nThomas B. R
 olinger (University of Maryland, Laboratory for Physical Sciences at Unive
 rsity of Maryland) and Christopher D. Krieger (Laboratory for Physical Sci
 ences at University of Maryland)\n---------------------\nWorkshop Morning 
 Break\n---------------------\nIntroduction - IA^3 2018:  8th Workshop on I
 rregular Applications: Architectures and Algorithms\n\nDue to the heteroge
 neous data sets they process, data intensive applications employ a diverse
  set of methods and data structures, exhibiting irregular memory accesses,
  control flows, and communication patterns. Current supercomputing systems
  are organized around components optimized for data localit...\n\n\nAntoni
 no Tumeo, John Feo, and Vito Giovanni Castellana (Pacific Northwest Nation
 al Laboratory)\n---------------------\nA Fast and Simple Approach to Merge
  and Merge Sorting Using Wide Vector Instructions\n\nMerging and sorting a
 lgorithms are the backbone of many modern computer applications. As such, 
 efficient implementations are desired. Recent architectural advancements i
 n CPUs (Central Processing Units), such as wider and more powerful vector 
 instructions, allow for algorithmic improvements. This pa...\n\n\nAlex Wat
 kins and Oded Green (Georgia Institute of Technology)\n-------------------
 --\nPhotonic Interconnects for Extreme Scale Computing\n\nThe capabilities
  of large-scale high performance computing systems, either as supercompute
 rs or warehouse scale data centers, are increasingly pervasive in differen
 t areas of modern life, from weather predictions to film and fashion recom
 mendations. New applications using data intensive computations...\n\n\nMad
 eleine Glick (Columbia University)\n---------------------\nMix-and-Match: 
 A Model-Driven Runtime Optimization Strategy for BFS on GPUs\n\nIt is univ
 ersally accepted that the performance of graph algorithms is heavily depen
 dent on the algorithm, the execution platform, and the structure of the in
 put graph. This variability remains difficult to predict and hinders the c
 hoice of the right algorithm for a given problem.\n\nIn this work, we ...\
 n\n\nMerijn Elwin Verstraaten, Ana Lucia Varbanescu, and Cees de Laat (Uni
 versity of Amsterdam)\n---------------------\nScale-Free Graph Processing 
 on a NUMA Machine\n\nModern shared-memory systems embrace the NUMA archite
 cture which has proven to be more scalable than the SMP architecture. In m
 any ways, a NUMA system resembles a shared-nothing distributed system: phy
 sically distinct processing units and memory regions. Memory accesses to r
 emote NUMA domains are mo...\n\n\nTanuj K. Aasawat, Tahsin Reza, and Matei
  Ripeanu (University of British Columbia)\n---------------------\nHigh-Per
 formance GPU Implementation of PageRank with Reduced Precision Based on Ma
 ntissa Segmentation\n\nWe address the acceleration of the PageRank algorit
 hm for web information retrieval on graphics processing units (GPUs) via a
  modular precision framework that adapts the input data format in memory t
 o the numerical requirements as the iteration converges. In detail, we aba
 ndon the ieee 754 single- a...\n\n\nThomas Grützmacher and Hartwig Anzt (
 Karlsruhe Institute of Technology), Florian Scheidegger (ETH Zurich), and 
 Enrique S. Quintana-Ortí (Jaume I University)\n---------------------\nVers
 al: The New Xilinx Adaptive Compute Acceleration Platforms (ACAP)\n\nIn th
 is presentation, I will present the new Adaptive Compute Acceleration Plat
 form. I will show the overall system architecture of the family of devices
  including the Arm cores (scalar engines), the programmable logic (Adaptab
 le Engines) and the new vector processor cores (AI engines). I will focus.
 ..\n\n\nKees Vissers (Xilinx Inc)\n\nTag: Architectures, Data Analytics, G
 raph Algorithms\n\nRegistration Category: Workshop Reg Pass\n\nSession Cha
 irs: Vito Giovanni Castellana (Pacific Northwest National Laboratory (PNNL
 )), John Feo (Pacific Northwest National Laboratory (PNNL)), and Antonino 
 Tumeo (Pacific Northwest National Laboratory (PNNL))
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