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DTSTART:19700308T020000
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DTSTAMP:20260522T150128Z
LOCATION:D172
DTSTART;TZID=America/Chicago:20181112T141000
DTEND;TZID=America/Chicago:20181112T150000
UID:submissions.supercomputing.org_SC18_sess168_pec331@linklings.com
SUMMARY:Versal: The New Xilinx Adaptive Compute Acceleration Platforms (AC
 AP)
DESCRIPTION:Kees Vissers (Xilinx Inc)\n\nIn this presentation, I will pres
 ent the new Adaptive Compute Acceleration Platform. I will show the overal
 l system architecture of the family of devices including the Arm cores (sc
 alar engines), the programmable logic (Adaptable Engines) and the new vect
 or processor cores (AI engines). I will focus on the new AI engines in mor
 e detail and show the concepts for the programming environment, the archit
 ecture, the integration in the total device, and some application domains,
  including Machine Learning and 5G wireless applications. I will illustrat
 e the initial design rationale and the architecture trade-offs. These plat
 forms extend the concept of tuning the memory hierarchy to the problem.\n\
 nTag: Architectures, Data Analytics, Graph Algorithms\n\nRegistration Cate
 gory: Workshop Reg Pass\n\nSession Chairs: Vito Giovanni Castellana (Pacif
 ic Northwest National Laboratory (PNNL)), John Feo (Pacific Northwest Nati
 onal Laboratory (PNNL)), and Antonino Tumeo (Pacific Northwest National La
 boratory (PNNL))\n\n
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