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DTSTAMP:20260522T150116Z
LOCATION:D172
DTSTART;TZID=America/Chicago:20181112T103000
DTEND;TZID=America/Chicago:20181112T105500
UID:submissions.supercomputing.org_SC18_sess168_ws_ia108@linklings.com
SUMMARY:Software Prefetching for Unstructured Mesh Applications
DESCRIPTION:Ioan Hadade (Oxford Thermofluids Institute, University of Oxfo
 rd); Timothy M. Jones (University of Cambridge); and Feng Wang and Luca di
  Mare (Oxford Thermofluids Institute, University of Oxford)\n\nApplication
 s that exhibit regular memory access patterns usually benefit transparentl
 y from hardware prefetchers that bring data into the fast on-chip cache ju
 st before it is required, thereby avoiding expensive cache misses. In cont
 rast, unstructured mesh applications contain irregular access patterns tha
 t are often more difficult to identify in hardware. An alternative for suc
 h workloads is software prefetching, where special non-blocking instructio
 ns load data into the cache hierarchy. However, there are currently few ex
 amples in the literature on how to incorporate such software prefetches in
 to existing applications with positive results.\n\nThis paper addresses th
 ese issues by demonstrating the utility and implementation of software pre
 fetching in an unstructured finite volume CFD code of representative size 
 and complexity to an industrial application and across a number of process
 ors. We present the benefits of auto-tuning for finding the optimal prefet
 ch distance values across different computational kernels and architecture
 s and demonstrate the importance of choosing the right prefetch destinatio
 n across the available cache levels for best performance. We discuss the i
 mpact of the data layout on the number of prefetch instructions required i
 n kernels with indirect-access patterns and show how to integrate them on 
 top of existing optimizations such as vectorization. Through this we show 
 significant full application speed-ups on a range of processors, such as t
 he Intel Xeon Skylake CPU (15%) as well as on the in-order Intel Xeon Phi 
 Knights Corner (1.99X) architecture and the out-of-order Knights Landing (
 33%) many-core processor.\n\nTag: Architectures, Data Analytics, Graph Alg
 orithms\n\nRegistration Category: Workshop Reg Pass\n\nSession Chairs: Vit
 o Giovanni Castellana (Pacific Northwest National Laboratory (PNNL)), John
  Feo (Pacific Northwest National Laboratory (PNNL)), and Antonino Tumeo (P
 acific Northwest National Laboratory (PNNL))\n\n
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