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LOCATION:D167/174
DTSTART;TZID=America/Chicago:20181111T090000
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UID:submissions.supercomputing.org_SC18_sess170@linklings.com
SUMMARY:Fourth International Workshop on Heterogeneous High-Performance Re
 configurable Computing (H2RC'18)
DESCRIPTION:Workshop Morning Break\n---------------------\nSimBSP: Enablin
 g RTL Simulation for Intel FPGA OpenCL Kernels\n\nRTL simulation is an int
 egral step in FPGA development since it provides cycle accurate informatio
 n regarding the behavior and performance of custom architectures, without 
 having to compile the design to actual hardware. Despite its advantages, h
 owever, RTL simulation is not currently supported by a...\n\n\nMartin C. H
 erbordt and Ahmed Sanaullah (Boston University)\n---------------------\nFi
 rst Steps in Porting the LFRic Weather and Climate Model to the FPGAs of t
 he EuroExa Architecture\n\nThe EuroExa project proposes a High-Performance
  Computing (HPC) architecture which is both scalable to exascale performan
 ce levels and delivers world-leading power efficiency. This is achieved th
 rough the use of low-power ARM processors accelerated by closely-coupled F
 PGA programmable components. In...\n\n\nMike Ashworth, Graham Riley, Andre
 w Attwood, and John Mawer (University of Manchester)\n--------------------
 -\nPreserving Privacy through Processing Encrypted Data\n\nSecure Function
  Evaluation (SFE) allows an interested party to evaluate a function over p
 rivate data without learning anything about the inputs other than the outc
 ome of this computation. This offers a strong privacy guarantee: SFE enabl
 es, e.g., a medical researcher, a statistician, or a data analy...\n\n\nMi
 riam Leeser (Northeastern University)\n---------------------\nAccelerating
  Intelligence\n\nMassive amounts of data are being consumed and processed 
 to drive business. The exponential increase in data has not been matched b
 y the computational power of processors. This has led to the rise of accel
 erators. However, big data algorithms for ETL, ML, AI, and DL are evolving
  rapidly and/or have ...\n\n\nJohn Davis (Bigstream Networks)\n-----------
 ----------\nIntroduction - Fourth International Workshop on Heterogeneous 
 High-Performance Reconfigurable Computing (H2RC'18)\n\nAs in the previous 
 three years, this workshop will bring together application experts, softwa
 re developers, and hardware engineers, both from industry and academia, to
  share experiences and best practices to leverage the practical applicatio
 n of reconfigurable logic to Scientific Computing, Machine/...\n\n\nJason 
 Bakos (University of South Carolina), Michaela Blott (Xilinx Inc), Torsten
  Hoefler (ETH Zurich), and Franck Cappello (Argonne National Laboratory)\n
 ---------------------\nBringing FPGAs to HPC Production Systems and Codes\
 n\nFPGA architectures and development tools have made great strides toward
 s a platform for high-performant and energy-efficient computing, competing
  head to head with other processor and accelerator technologies. While we 
 have seen the first large-scale deployments of FPGAs in public and private
  clouds...\n\n\nChristian Plessl (Paderborn University)\n-----------------
 ----\nIntegrating Network-Attached FPGAs into the Cloud Using Partial Reco
 nfiguration\n\nBurkhard Ringlein (IBM Zurich Research Laboratory, Universi
 ty of Erlangen-Nuremberg); Francois Abel (IBM Zurich Research Laboratory);
  and Alexander Ditter (University of Erlangen-Nuremberg)\n----------------
 -----\nThe MANGO Process for Designing and Programming Multi-Accelerator M
 ulti-FPGA Systems\n\nThis paper describes the approach followed in the Eur
 opean FETHPC MANGO project to design and program systems made of multiple 
 FPGAs interconnected. The MANGO approach relies on the instantiation and m
 anagement of multiple generic and custom-made accelerators which can be pr
 ogrammed to communicate e...\n\n\nRafael Tornero, Jose Flich, Jose Maria M
 artinez, and Tomás Picornell (Technical University of Valencia) and Vincen
 zo Scotti (University of Naples Federico II)\n---------------------\nScala
 ble FPGA Deployments for HPC and DC Applications\n\nFPGAs have recently fo
 und their way and niche in large-scale data-center (DC) applications, eg, 
 for endpoint encryption/compression, video transcoding, and genomics appli
 cations. We present two research projects that address two remaining roadb
 locks on the way to scalable performance and energy-effi...\n\n\nChristoph
  Hagleitner (IBM)\n---------------------\nStream Computing of Lattice-Bolt
 zmann Method on Intel Programmable Accelerator Card\n\nIntel Programmable 
 Accelerator Card (Intel-PAC) and Open Programmable Acceleration Engine (OP
 AE) aim at saving developers time and enabling code re-use across multiple
  FPGA platforms. We implemented a Lattice-Boltzmann Method (LBM) computing
  core, a computational fluid dynamics application, on Intel...\n\n\nTakaak
 i Miyajima, Tomohiro Ueno, and Kentaro Sano (RIKEN)\n\nTag: Accelerators, 
 Heterogeneous Systems, NVRAM\n\nRegistration Category: Workshop Reg Pass
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