BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Chicago
X-LIC-LOCATION:America/Chicago
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260522T150116Z
LOCATION:D167/174
DTSTART;TZID=America/Chicago:20181111T103000
DTEND;TZID=America/Chicago:20181111T104500
UID:submissions.supercomputing.org_SC18_sess170_ws_h2rc115@linklings.com
SUMMARY:SimBSP: Enabling RTL Simulation for Intel FPGA OpenCL Kernels
DESCRIPTION:Martin C. Herbordt and Ahmed Sanaullah (Boston University)\n\n
 RTL simulation is an integral step in FPGA development since it provides c
 ycle accurate information regarding the behavior and performance of custom
  architectures, without having to compile the design to actual hardware. D
 espite its advantages, however, RTL simulation is not currently supported 
 by a number of commercial FPGA OpenCL toolflows, including Intel OpenCL SD
 K for FPGAs (IOCLF). Obtaining reliable performance values for OpenCL kern
 els requires a full compilation to hardware, while emulation can only prov
 ide functional verification of the C code. Thus, development and optimizat
 ion time-frames for IOCLF designs can be on the order of days, even for si
 mple applications. In this work, we present our custom Board Support Packa
 ge for IOCLF, called SimBSP, which enables OpenCL kernels to be compiled f
 or RTL simulation. \n\nWe provide details regarding the standard kernel po
 rts created by the IOCLF compiler, which can be used by testbenches to int
 erface the generated design. We also list the addresses and descriptions o
 f configuration registers that are used to set kernel parameters and provi
 de a start trigger. Finally, we present details of SimBSP toolflow, which 
 is integrated into the standard IOCLF and automates the process of generat
 ing kernel HDL and testbenches, and setting up the simulation environment.
  Our work on SimBSP will be made available Open Source to drive a communit
 y effort towards further improving the toolflow.\n\nTag: Accelerators, Het
 erogeneous Systems, NVRAM\n\nRegistration Category: Workshop Reg Pass\n\n
END:VEVENT
END:VCALENDAR