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DTSTAMP:20260522T150115Z
LOCATION:C146
DTSTART;TZID=America/Chicago:20181114T110000
DTEND;TZID=America/Chicago:20181114T113000
UID:submissions.supercomputing.org_SC18_sess183_pap338@linklings.com
SUMMARY:Runtime-Assisted Cache Coherence Deactivation in Task Parallel Pro
 grams
DESCRIPTION:Paul Caheny (Barcelona Supercomputing Center, Polytechnic Univ
 ersity of Catalonia); Lluc Alvarez (Barcelona Supercomputing Center); Mate
 o Valero and Miquel Moretó (Barcelona Supercomputing Center, Polytechnic U
 niversity of Catalonia); and Marc Casas (Barcelona Supercomputing Center)\
 n\nWith increasing core counts, the scalability of directory-based cache c
 oherence has become a challenging problem. To reduce the area and power ne
 eds of the directory, recent proposals reduce its size by classifying data
  as private or shared, and disable coherence for private data. However, ex
 isting classification methods suffer from inaccuracies and require complex
  hardware support with limited scalability.\n\nThis paper proposes a hardw
 are/software co-designed approach: the runtime system identifies data that
  is guaranteed by the programming model semantics to not require coherence
  and notifies the microarchitecture. The microarchitecture deactivates coh
 erence for this private data and powers off unused directory capacity. Our
  proposal reduces directory accesses to just 26% of the baseline system an
 d supports a 64× smaller directory with only 2.8% performance degradation.
  By dynamically calibrating the directory size, our proposal saves 86% of 
 dynamic energy consumption in the directory without harming performance.\n
 \nTag: Algorithms, Architectures, Memory, Networks, Parallel Programming L
 anguages, Libraries, and Models, Power, Programming Systems, Scheduling\n\
 nRegistration Category: Tech Program Reg Pass\n\nSession Chair: Patrick S.
  McCormick (Los Alamos National Laboratory (LANL))\n\n
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