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DTSTART:19700308T020000
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DTSTAMP:20260522T150116Z
LOCATION:C140/142
DTSTART;TZID=America/Chicago:20181113T103000
DTEND;TZID=America/Chicago:20181113T110000
UID:submissions.supercomputing.org_SC18_sess194_pap147@linklings.com
SUMMARY:Exploiting Idle Resources in a High-Radix Switch for Supplemental 
 Storage
DESCRIPTION:Matthias A. Blumrich, Nan Jiang, and Larry R. Dennison (Nvidia
  Corporation)\n\nA general-purpose switch for a high-performance network i
 s usually designed with symmetric ports providing credit-based flow contro
 l and error recovery via link-level retransmission. Because port buffers m
 ust be sized for the longest links and modern asymmetric network topologie
 s have a wide range of link lengths, we observe that there can be a signif
 icant amount of unused buffer memory, particularly in edge switches. We al
 so observe that the tiled architecture used in many high-radix switches co
 ntains an abundance of internal bandwidth. We combine these observations t
 o create a new switch architecture that allows ports to stash packets in u
 nused buffers on other ports, accessible via excess internal bandwidth in 
 the tiled switch. We explore this architecture through two use cases: end-
 to-end resilience and congestion mitigation. We find that stashing is high
 ly effective and does not negatively impact network performance.\n\nTag: A
 rchitectures, Data Analytics, Networks\n\nRegistration Category: Tech Prog
 ram Reg Pass\n\nFinalist: BP Finalist\n\nSession Chair: Madeleine Glick (C
 olumbia University)\n\n
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