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DTSTAMP:20260522T150119Z
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DTSTART;TZID=America/Chicago:20181114T153000
DTEND;TZID=America/Chicago:20181114T160000
UID:submissions.supercomputing.org_SC18_sess215_pap431@linklings.com
SUMMARY:Associative Instruction Reordering to Alleviate Register Pressure
DESCRIPTION:Prashant Singh Rawat, Aravind Sukumaran-Rajam, and Atanas Roun
 tev (Ohio State University); Fabrice Rastello (French Institute for Resear
 ch in Computer Science and Automation (INRIA)); Louis-Noel Pouchet (Colora
 do State University); and P. Sadayappan (Ohio State University)\n\nRegiste
 r allocation is generally considered a practically solved problem. For mos
 t applications, the register allocation strategies in production compilers
  are very effective in controlling the number of loads/stores and register
  spills. However, existing register allocation strategies are not effectiv
 e and result in excessive register spilling for computation patterns with 
 a high degree of many-to-many data reuse, e.g., high-order stencils and te
 nsor contractions.  We develop a source-to-source instruction reordering s
 trategy that exploits the flexibility of reordering associative operations
  to alleviate register pressure.  The developed transformation module impl
 ements an adaptable strategy that can appropriately control the degree of 
 instruction-level parallelism, while relieving register pressure.  The eff
 ectiveness of the approach is demonstrated through experimental results us
 ing multiple production compilers (GCC, Clang/LLVM) and target platforms (
 Intel Xeon Phi, and Intel x86 multi-core).\n\nTag: Algorithms, Application
 s, Architectures, Compiler Analysis and Optimization, Floating Point, Perf
 ormance, Precision, Programming Systems, Tools\n\nRegistration Category: T
 ech Program Reg Pass\n\nSession Chair: Protonu Basu (NVIDIA)\n\n
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