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DTSTART:19700308T020000
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DTSTAMP:20260522T150116Z
LOCATION:C141/143/149
DTSTART;TZID=America/Chicago:20181114T160000
DTEND;TZID=America/Chicago:20181114T163000
UID:submissions.supercomputing.org_SC18_sess215_pap464@linklings.com
SUMMARY:Harnessing GPU's Tensor Cores Fast FP16 Arithmetic to Speedup Mixe
 d-Precision Iterative Refinement Solvers
DESCRIPTION:Azzam Haidar (University of Tennessee, Innovative Computing La
 boratory); Stan Tomov and Jack Dongarra (University of Tennessee); and Nic
 holas Higham (University of Manchester, School of Mathematics)\n\nThe use 
 of low-precision arithmetic in computing methods has been a powerful tool 
 to accelerate numerous scientific computing applications including Artific
 ial Intelligence. We present an investigation showing that other HPC appli
 cations can harness this power too, and in particular, the general HPC pro
 blem of solving Ax = b, where A is a large dense matrix, and the solution 
 is needed in FP64 accuracy. Our approach is based on the mixed-precision (
 FP16->FP64) iterative refinement technique – we generalize and extend prio
 r advances into a framework, for which we develop architecture-specific al
 gorithms and highly-tuned implementations where we show how the use of FP1
 6-TC (tensor cores) arithmetic can provide up to 4X speedup and improve th
 e energy consumption by a factor of 5 achieving 74 Gflop/Watt. This is due
  to the performance boost that the FP16 (Tensor Cores) provide and to its 
 better accuracy that outperforms the classical FP16.\n\nTag: Algorithms, A
 pplications, Architectures, Compiler Analysis and Optimization, Floating P
 oint, Performance, Precision, Programming Systems, Tools\n\nRegistration C
 ategory: Tech Program Reg Pass\n\nSession Chair: Protonu Basu (NVIDIA)\n\n
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