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DTSTART:19700308T020000
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DTSTAMP:20260522T150117Z
LOCATION:C146
DTSTART;TZID=America/Chicago:20181114T133000
DTEND;TZID=America/Chicago:20181114T140000
UID:submissions.supercomputing.org_SC18_sess216_pap392@linklings.com
SUMMARY:Lessons Learned from Memory Errors Observed Over the Lifetime of C
 ielo
DESCRIPTION:Scott Levy and Kurt B. Ferreira (Sandia National Laboratories)
 , Nathan DeBardeleben (Los Alamos National Laboratory), Taniya Siddiqua an
 d Vilas Sridharan (Advanced Micro Devices Inc), and Elisabeth Baseman (Los
  Alamos National Laboratory)\n\nMaintaining the performance of high-perfor
 mance computing (HPC) applications as failures increase is a major challen
 ge for next-generation extreme-scale systems. Recent research demonstrates
  that hardware failures are expected to become more common due to increase
 d component counts, reduced device-feature sizes, and tightly-constrained 
 power budgets. Few existing studies, however, have examined failures in th
 e context of the entire lifetime of a single platform. In this paper, we a
 nalyze failure data collected over the entire lifetime of Cielo, a leaders
 hip-class HPC system. Our analysis reveals several key findings, including
 : (i) Cielo’s memory (DRAM and SRAM) exhibited no discernible aging effect
 s; (ii) correctable memory faults are not predictive of future uncorrectab
 le memory faults; (iii) developing more comprehensive logging facilities w
 ill improve failure analysis on future machines; (iv) continued advances w
 ill be required to ensure current failure mitigation techniques remain a v
 iable option for future platforms.\n\nTag: Performance, Resiliency, Tools\
 n\nRegistration Category: Tech Program Reg Pass\n\nSession Chair: Michèle 
 Weiland (EPCC, The University of Edinburgh; The University of Edinburgh)\n
 \n
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