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DTSTART;TZID=America/Chicago:20181111T133000
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UID:submissions.supercomputing.org_SC18_sess250_tut147@linklings.com
SUMMARY:Productive Parallel Programming for FPGA with High-Level Synthesis
DESCRIPTION:Johannes de Fine Licht and Torsten Hoefler (ETH Zurich)\n\nAs 
 the scale of large high performance computing systems increases, so does t
 heir power consumption, making energy efficiency a first class citizen in 
 their design. While GPUs and custom processors have improved this situatio
 n significantly, reconfigurable architectures, such as FPGAs, promise anot
 her major step in energy efficiency, constituting a middle ground between 
 fixed hardware architectures and custom-built ASICs. \n\nProgramming FPGAs
  has traditionally been done in hardware description languages, requiring 
 extensive hardware knowledge and significant engineering effort.  This tut
 orial shows how high-level synthesis (HLS) can be harnessed to productivel
 y achieve scalable pipeline parallelism on FPGAs. Attendees will learn how
  to target FPGA resources from high-level C++ or OpenCL code, guiding the 
 mapping from imperative code to hardware, enabling them to develop massive
 ly parallel designs with real performance benefits. \nWe treat concrete ex
 amples well known from the software world, relating traditional code optim
 izations to both corresponding and new transformations for hardware, build
 ing on existing knowledge when introducing new topics. By bridging the gap
  between software and hardware optimization, our tutorial aims to enable d
 evelopers from a larger set of backgrounds to start tapping into the poten
 tial of FPGAs with real high performance codes.\n\nTag: Heterogeneous Syst
 ems, Parallel Programming Languages, Libraries, and Models\n\nRegistration
  Category: Tutorial Reg Pass\n\n
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