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DTSTAMP:20260522T150117Z
LOCATION:C156
DTSTART;TZID=America/Chicago:20181111T083000
DTEND;TZID=America/Chicago:20181111T170000
UID:submissions.supercomputing.org_SC18_sess257_tut189@linklings.com
SUMMARY:Node-Level Performance Engineering
DESCRIPTION:Georg Hager (University of Erlangen-Nuremberg, Erlangen Region
 al Computing Center) and Gerhard Wellein (University of Erlangen-Nuremberg
 , Department of Computer Science)\n\nThe advent of multi- and manycore chi
 ps has led to a further opening of the gap between peak and application pe
 rformance for many scientific codes. This trend is accelerating as we move
  from petascale to exascale. Paradoxically, bad node-level performance hel
 ps to "efficiently" scale to massive parallelism, but at the price of incr
 eased overall time to solution. If the user cares about time to solution o
 n any scale, optimal performance on the node level is often the key factor
 . We convey the architectural features of current processor chips, multipr
 ocessor nodes, and accelerators, as far as they are relevant for the pract
 itioner. Peculiarities like SIMD vectorization, shared vs. separate caches
 , bandwidth bottlenecks, and ccNUMA characteristics are introduced, and th
 e influence of system topology and affinity on the performance of typical 
 parallel programming constructs is demonstrated. Performance engineering a
 nd performance patterns are suggested as powerful tools that help the user
  understand the bottlenecks at hand and to assess the impact of possible c
 ode optimizations. A cornerstone of these concepts is the roofline model, 
 which is described in detail, including useful case studies, limits of its
  applicability, and possible refinements.\n\nTag: Heterogeneous Systems, P
 erformance\n\nRegistration Category: Tutorial Reg Pass\n\n
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