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RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
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BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
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RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
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DTSTART;TZID=America/Chicago:20181115T110000
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UID:submissions.supercomputing.org_SC18_sess270_exforum137@linklings.com
SUMMARY:Enabling High Performance Memory for the Broad HPC markets
DESCRIPTION:Andreas Schlapka (Micron Technology Inc)\n\nHigh performance c
 ompute demands advanced memory solutions. Designing for maximum performanc
 e has traditionally carried the burden of substantial investment in cost a
 nd time to implement "in package memory on silicon substrates". Early in 2
 018 Micron has introduced new technology being adopted across markets for 
 performance solutions. Memory performance required for applications like n
 etworking routing and switching, autonomous driving, Crypto mining, Gaming
  Consoles, Graphics cards, and HPC acceleration.  In this discussion, Micr
 on will outline packaged memory solutions, with bandwidth required for HPC
  applications with the ecosystem enablement and adoption deployed in produ
 ction. For the HPC community, this is provide an easy implementation of hi
 gh performance solutions.\n\nTag: Architectures, Memory, Storage\n\nSessio
 n Chair: Paul Peltz (Oak Ridge National Laboratory (ORNL))\n\n
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