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DTSTART:19700308T020000
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DTSTAMP:20260522T150128Z
LOCATION:D171
DTSTART;TZID=America/Chicago:20181114T113000
DTEND;TZID=America/Chicago:20181114T120000
UID:submissions.supercomputing.org_SC18_sess271_exforum139@linklings.com
SUMMARY:Accelerate Machine Learning with High Performance Memory
DESCRIPTION:Mark Hur (Micron Technology Inc)\n\nMachine learning is drivin
 g the next industrial revolution, through the use of easy to program accel
 erator boards, you can be in the driver seat. In this talk, Micron will di
 scuss a new novel inference engine architecture that provides the benefits
  of hardware acceleration, that supports a wide range of ML frameworks and
  networks; and is software programmable.  This new architecture/platform i
 s a flexible and programmable neural network accelerator co-processor is d
 esigned for 1) maximum hardware utilization, 2) efficient memory bandwidth
  usage, 3) ultra-low power operation.  This architecture coupled with a ML
  complier allows the user to take advantage of hardware acceleration while
  maintaining software programmability.\n\nTag: Machine Learning, Scientifi
 c Computing\n\nSession Chair: Scott Michael (Indiana University)\n\n
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