BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Chicago
X-LIC-LOCATION:America/Chicago
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260522T150116Z
LOCATION:D221
DTSTART;TZID=America/Chicago:20181113T153000
DTEND;TZID=America/Chicago:20181113T164500
UID:submissions.supercomputing.org_SC18_sess279@linklings.com
SUMMARY:Doctoral Showcase III
DESCRIPTION:Designing High-Performance, Resilient, and Heterogeneity-Aware
  Key-Value Storage for Modern HPC Clusters\n\nDistributed key-value stores
  are being increasingly used to accelerate Big Data workloads on modern HP
 C clusters. The advances in HPC technologies (e.g., RDMA, SSDs) has direct
 ed several efforts towards employing hybrid storage with RDMA, for designi
 ng high- performance key-value stores. With this a...\n\n\nDipti Shankar, 
 Dhabaleswar K. Panda, and Xiaoyi Lu (Ohio State University)\n-------------
 --------\nHigh Performance Middlewares for Next Generation Architectures: 
 Challenges and Solutions\n\nThe emergence of modern multi-/many-core archi
 tectures and high-performance interconnects have fueled the growth of larg
 e-scale supercomputing clusters. Due to this unprecedented growth in scale
  and compute density, high performance computing (HPC) middlewares now fac
 e a plethora of new challenges t...\n\n\nSourav Chakraborty and Dhabaleswa
 r K. Panda (Ohio State University)\n---------------------\nHardware Transa
 ctional Persistent Memory\n\nThis research solves the problem of creating 
 durable transactions in byte-addressable Non-Volatile Memory or Persistent
  Memory (PM) when using Hardware Transactional Memory (HTM)-based concurre
 ncy control.  It shows how HTM transactions can be ordered correctly and a
 tomically into PM by the use...\n\n\nEllis Giles and Peter Varman (Rice Un
 iversity)\n---------------------\nThe Algorithm and Framework Designs and 
 Optimizations for Scalable Automata Processing on HPC Platforms\n\nAutomat
 a processing could perform as the core of many applications in the areas s
 uch as network security, text mining, and bioinformatics. Achieving high-s
 peed and scalable automata processing is exceptionally challenging. For on
 e thing, the classic DFA representation is memory-bandwidth efficient b...
 \n\n\nXiaodong Yu and Danfeng Yao (Virginia Tech)\n---------------------\n
 Efficient Deployment of Irregular Computations on Multi- and Many-Core Arc
 hitectures\n\nMulti- and manycore processors have been advancing High Perf
 ormance Computing with their high throughput and power efficiency. There h
 as been an increasing interest in accelerating irregular computations on t
 hese devices that offer massive parallelism. My thesis focuses on compiler
  techniques and co...\n\n\nHancheng Wu and Michela Becchi (North Carolina 
 State University)\n\nTag: Architectures, Memory, Runtime Systems, Storage,
  Doctoral Showcase\n\nRegistration Category: Workshop Reg Pass, Tutorial R
 eg Pass, Tech Program Reg Pass, Exhibits Reg Pass, Exhibits - Exhibit Hall
  Only Reg Pass\n\nSession Chair: Sanjukta Bhowmick (University of North Te
 xas)
END:VEVENT
END:VCALENDAR