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DTSTART:19700308T020000
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DTSTAMP:20260522T150123Z
LOCATION:D221
DTSTART;TZID=America/Chicago:20181113T161500
DTEND;TZID=America/Chicago:20181113T163000
UID:submissions.supercomputing.org_SC18_sess279_drs118@linklings.com
SUMMARY:Hardware Transactional Persistent Memory
DESCRIPTION:Ellis Giles and Peter Varman (Rice University)\n\nThis researc
 h solves the problem of creating durable transactions in byte-addressable 
 Non-Volatile Memory or Persistent Memory (PM) when using Hardware Transact
 ional Memory (HTM)-based concurrency control.  It shows how HTM transactio
 ns can be ordered correctly and atomically into PM by the use of a novel s
 oftware protocol.  We exploit the ordering mechanism to design a novel per
 sistence method that decouples HTM concurrency from back-end PM operations
 .  Failure atomicity is achieved using redo logging coupled with aliasing 
 to guard against mistimed cache evictions.<br /><br />The algorithm uses e
 fficient lock-free mechanisms with bounded static memory requirements and 
 executes on existing Intel based processors.  A back-end distributed memor
 y controller alternative provides a hardware implementation choice for cat
 ching PM cache evictions.  Our approach compares well with standard (volat
 ile) HTM transactions and yields significant gains in latency and throughp
 ut over other persistence methods.\n\nTag: Architectures, Memory, Runtime 
 Systems, Storage, Doctoral Showcase\n\nRegistration Category: Workshop Reg
  Pass, Tutorial Reg Pass, Tech Program Reg Pass, Exhibits Reg Pass, Exhibi
 ts - Exhibit Hall Only Reg Pass\n\nSession Chair: Sanjukta Bhowmick (Unive
 rsity of North Texas)\n\n
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