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DTSTART:19700308T020000
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DTSTAMP:20260522T150111Z
LOCATION:C2/3/4 Ballroom
DTSTART;TZID=America/Chicago:20181115T083000
DTEND;TZID=America/Chicago:20181115T170000
UID:submissions.supercomputing.org_SC18_sess324_post113@linklings.com
SUMMARY:Hardware Acceleration of CNNs with Coherent FPGAs
DESCRIPTION:Md Syadus Sefat, Semih Aslan, and Apan Qasem (Texas State Univ
 ersity)\n\nThis paper describes a new flexible approach to implementing en
 ergy-efficient CNNs on FPGAs. Our design leverages the Coherent Accelerato
 r Processor Interface (CAPI) which provides a cache-coherent view of syste
 m memory to attached accelerators. Convolution layers are formulated as ma
 trix multiplication kernels and then accelerated on CAPI-supported Kintex 
 FPGA board. Our implementation bypasses the need for device driver code an
 d significantly reduces the communication and I/O transfer overhead. To im
 prove the performance of the entire application, not just the convolution 
 layers, we propose a collaborative model of execution in which the control
  of the data flow within the accelerator is kept independent, freeing-up C
 PU cores to work on other parts of the application. For further performanc
 e enhancements, we propose a technique to exploit data locality in the cac
 he, situated in the CAPI Power Service Layer (PSL). Finally, we develop a 
 resource-conscious implementation for more efficient utilization of resour
 ces and improved scalability.\n\nRegistration Category: Tech Program Reg P
 ass, Exhibits Reg Pass\n\n
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