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DTSTAMP:20260522T150111Z
LOCATION:C2/3/4 Ballroom
DTSTART;TZID=America/Chicago:20181115T083000
DTEND;TZID=America/Chicago:20181115T170000
UID:submissions.supercomputing.org_SC18_sess324_post160@linklings.com
SUMMARY:Energy Efficiency of Reconfigurable Caches on FPGAs
DESCRIPTION:Tianqi Wang (Boston University), Ang Li (Pacific Northwest Nat
 ional Laboratory), and Tong Geng and Martin Herbordt (Boston University)\n
 \nThe performance of a given cache architecture depends largely on the app
 lications that run on it. Even though each application has its best-suited
  cache configuration, vendors of fixed HPC systems must provide compromise
  designs. Reconfigurable caches can adjust cache configuration dynamically
  to get best-suited cache parameters in runtime and notably reduce energy 
 consumption.  For example, when it is possible to deploy a low capacity lo
 w associativity design without increasing the miss rate substantially. For
  modern multi-core processors, each core's memory access behavior can be i
 nfluenced by other cores. So it is more complicated to design reconfigurab
 le caches for them. \n\nIn this paper, a design for a reconfigurable cache
  on FPGAs is presented that can run in modes with different capacities, as
 sociativity. We demonstrate that better performance and energy efficiency 
 can be achieved by tuning these cache parameters at runtime.\n\nRegistrati
 on Category: Tech Program Reg Pass, Exhibits Reg Pass\n\n
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