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DTSTART:19700308T020000
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DTSTAMP:20260522T150110Z
LOCATION:C2/3/4 Ballroom
DTSTART;TZID=America/Chicago:20181114T083000
DTEND;TZID=America/Chicago:20181114T170000
UID:submissions.supercomputing.org_SC18_sess326_spost136@linklings.com
SUMMARY:Hardware Transactional Persistent Memory
DESCRIPTION:Ellis Giles (Rice University)\n\nThis research solves the prob
 lem of creating durable transactions in byte-addressable Non-Volatile Memo
 ry or Persistent Memory (PM) when using Hardware Transactional Memory (HTM
 )-based concurrency control.  It shows how HTM transactions can be ordered
  correctly and atomically into PM by the use of a novel software protocol.
   We exploit the ordering mechanism to design a novel persistence method t
 hat decouples HTM concurrency from back-end PM operations.  Failure atomic
 ity is achieved using redo logging coupled with aliasing to guard against 
 mistimed cache evictions.\n\nThe algorithm uses efficient lock-free mechan
 isms with bounded static memory requirements and executes on existing Inte
 l based processors.  A back-end distributed memory controller alternative 
 provides a hardware implementation choice for catching PM cache evictions.
   Our approach compares well with standard (volatile) HTM transactions and
  yields significant gains in latency and throughput over other persistence
  methods.\n\nRegistration Category: Tech Program Reg Pass, Exhibits Reg Pa
 ss\n\n
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