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LOCATION:C2/3/4 Ballroom
DTSTART;TZID=America/Chicago:20181115T083000
DTEND;TZID=America/Chicago:20181115T170000
UID:submissions.supercomputing.org_SC18_sess327_spost118@linklings.com
SUMMARY:Mitigating Performance and Progress Variability in Iterative Async
 hronous Algorithms
DESCRIPTION:Justs Zarins (University of Edinburgh)\n\nLarge HPC machines a
 re susceptible to irregular performance. Factors like chip manufacturing d
 ifferences, heat management, and network congestion combine to result in v
 arying execution time for the same code and input sets. Asynchronous algor
 ithms offer a partial solution. In these algorithms, fast workers are not 
 forced to synchronize with slow ones. Instead they continue computing upda
 tes, and moving toward the solution, using the latest data available to th
 em, which may have become stale (i.e. a number of iterations out of date c
 ompared to the most recent data). While this allows for high computational
  efficiency, the convergence rate of asynchronous algorithms tends to be l
 ower.\n\nTo address this problem, we are using the unique properties of as
 ynchronous algorithms to develop load balancing strategies for iterative a
 synchronous algorithms in both shared and distributed memory. Our poster s
 hows how our solution attenuates noise, resulting in significant reduction
  progress imbalance and time-to-solution variability.\n\nRegistration Cate
 gory: Tech Program Reg Pass, Exhibits Reg Pass\n\n
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