BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Chicago
X-LIC-LOCATION:America/Chicago
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260522T150112Z
LOCATION:C2/3/4 Ballroom
DTSTART;TZID=America/Chicago:20181115T083000
DTEND;TZID=America/Chicago:20181115T170000
UID:submissions.supercomputing.org_SC18_sess341_drs118@linklings.com
SUMMARY:Hardware Transactional Persistent Memory
DESCRIPTION:Ellis Giles and Peter Varman (Rice University)\n\nThis researc
 h solves the problem of creating durable transactions in byte-addressable 
 Non-Volatile Memory or Persistent Memory (PM) when using Hardware Transact
 ional Memory (HTM)-based concurrency control.  It shows how HTM transactio
 ns can be ordered correctly and atomically into PM by the use of a novel s
 oftware protocol.  We exploit the ordering mechanism to design a novel per
 sistence method that decouples HTM concurrency from back-end PM operations
 .  Failure atomicity is achieved using redo logging coupled with aliasing 
 to guard against mistimed cache evictions.<br /><br />The algorithm uses e
 fficient lock-free mechanisms with bounded static memory requirements and 
 executes on existing Intel based processors.  A back-end distributed memor
 y controller alternative provides a hardware implementation choice for cat
 ching PM cache evictions.  Our approach compares well with standard (volat
 ile) HTM transactions and yields significant gains in latency and throughp
 ut over other persistence methods.\n\nRegistration Category: Workshop Reg 
 Pass, Tutorial Reg Pass, Tech Program Reg Pass, Exhibits Reg Pass, Exhibit
 s - Exhibit Hall Only Reg Pass\n\n
END:VEVENT
END:VCALENDAR