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BEGIN:VEVENT
DTSTAMP:20260522T150109Z
LOCATION:Booth 619
DTSTART;TZID=America/Chicago:20181113T100000
DTEND;TZID=America/Chicago:20181113T180000
UID:submissions.supercomputing.org_SC18_sess498_emt103@linklings.com
SUMMARY:Parallelware Analyzer: Speeding Up the Parallel Software Developme
 nt Lifecycle.
DESCRIPTION:Toni Collis (Appentra Solutions, Collis-Holmes Innovations Lim
 ited) and Manuel Arenaz, Javier Novo Rodríguez, Daniel Otero Oubiña, Jaime
  González Cuevas, and Belén Torrente Torrente (Appentra Solutions)\n\nPara
 llelware Analyzer is the second product in the Parallelware Tools Suite an
 d is being designed around the needs of the user.  Parallelware Analyzer i
 s a command line reporting tool designed to help the HPC application devel
 oper speed up their development process, and also provide the HPC service 
 provider a detailed understanding of what parallelization software solutio
 ns are being used on their systems. The tool enables the user to ‘zoom in’
  on what they need to know, providing key information for understanding hy
 brid MPI+X applications from the point of view of computations, memory and
  control flow. The reports will cover code features such as understanding 
 memory access patterns, data layout and data scoping; identifying function
 s free of side-effects beyond procedure boundaries; analyzing dependencies
  beyond loop boundaries to identify regions that are already parallelized 
 and computational patterns that offer parallelization opportunities; annot
 ating the source code with parallelization primitives including vectorizat
 ion, SIMD, multi-threading, offloading to accelerators etc. This is all do
 ne by static analysis of the source code using LLVM-based compiler technol
 ogy, without the need to ‘instrument’ or benchmark your code and can even 
 be run on your laptop, irrespective of how many cores your code is designe
 d to run on.\n\nRegistration Category: Tech Program Reg Pass, Exhibits Reg
  Pass, Exhibits - Exhibit Hall Only Reg Pass\n\n
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