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DTSTART:19700308T020000
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DTSTAMP:20260522T150109Z
LOCATION:Booth 619
DTSTART;TZID=America/Chicago:20181113T100000
DTEND;TZID=America/Chicago:20181113T180000
UID:submissions.supercomputing.org_SC18_sess498_emt104@linklings.com
SUMMARY:A Cost-Effective Flexible System Optimized for DNN and ML
DESCRIPTION:I-Hsin Chung (IBM) and Yomi Yeh, Andy Yang, and Brian Pan (H3 
 Platform Inc)\n\nHardware accelerators (e.g., GPU) are increasingly used f
 or compute-intensive tasks (e.g., AI and HPC). When multiple accelerator a
 nd storage devices are present, direct data paths between the devices bypa
 ssing the host memory may be used (P2P). Current P2P provided by NVIDIA CU
 DA driver is limited to the NVIDIA GPUs under the same PCIe root complex a
 nd only up to 9 GPUs allowed in the P2P communication. \n\nIn our design, 
 we used a simplified architecture as the basic building block. The new PCI
 e switch allows PCIe ID translation between different PCIe domains and cus
 tomized routing. Together with the PCIe Gen 4, the blocks can stack togeth
 er to scale out. This design is especially desired for the collective comm
 unications in DNN/ML and many HPC applications. Compared to other PCIe exp
 ansion enclosures, our design allows a CPU card installed to make the syst
 em self-sufficient/operational.\n \nOn the system software side, our solut
 ion breaks the 9-GPU under the same PCIe root complex limit and is not lim
 ited to NVIDIA GPUs. For example, the data can be transferred between NVMe
  storage and GPU memory directly.\n\nOverall the new design provides a mor
 e cost-effective, robust and flexible solution that is optimized for DNN/M
 L and HPC applications.\n\nRegistration Category: Tech Program Reg Pass, E
 xhibits Reg Pass, Exhibits - Exhibit Hall Only Reg Pass\n\n
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