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DTSTART:19700308T020000
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DTSTAMP:20260522T150153Z
LOCATION:Booth 619
DTSTART;TZID=America/Chicago:20181114T100000
DTEND;TZID=America/Chicago:20181114T180000
UID:submissions.supercomputing.org_SC18_sess499@linklings.com
SUMMARY:Emerging Technologies Showcase (Day 2)
DESCRIPTION:The Emerging Technologies track will examine innovative soluti
 ons that may significantly improve and extend the world of HPC in the next
  five to fifteen years. Consisting of carefully selected exhibits, Emergin
 g Technologies will showcase innovative technologies from industry, govern
 ment labs, or academia. Typically these technologies will be very early-st
 age and so not yet available from industry as products.\n\nEnergy Efficien
 t Computer in the Exascale Age\n\nAchieving exascale-level computing requi
 res innovations in all aspects of computing from novel chipset designs to 
 datacenter construction.  Exascale debates typically revolve around novel 
 architectures that would be capable of exascale computing. Importantly tho
 ugh, faster typically is synonymous wi...\n\n\nMatthew T. Ziegler (Lenovo)
 \n---------------------\nFlexLION: Scalable and Reconfigurable All-to-All 
 Photonic Interconnects\n\nWe propose FlexLION (Flexible Low-Latency Interc
 onnect Optical Network) to pursue energy-efficient, scalable, and reconfig
 urable all-to-all silicon photonic (SiPh) interconnects. FlexLION offers c
 ontention-less and arbitration-free all-to-all communication among selecte
 d nodes (processors or electro...\n\n\nRoberto Proietti, Xian Xiao, Sebast
 ian Werner, and Pouya Fotouhi (University of California, Davis); Jeff Mess
 ig (Enablence Technologies Inc); and S.J. Ben Yoo (University of Californi
 a, Davis)\n---------------------\nThe Data-Centric Future and Gen-Z's Next
  Generation Interconnect\n\nCurrent computer architectures allow for netwo
 rk and storage transfers to occur at much lower rates than memory transfer
 s, so they must have separate buses, control signals, and command structur
 es. Processors must wait endlessly for these transfers to finish or must f
 ind other work to do. A great de...\n\n\nKurtis Bowman (Gen-Z Consortium)\
 n---------------------\nA Cost-Effective Flexible System Optimized for DNN
  and ML\n\nHardware accelerators (e.g., GPU) are increasingly used for com
 pute-intensive tasks (e.g., AI and HPC). When multiple accelerator and sto
 rage devices are present, direct data paths between the devices bypassing 
 the host memory may be used (P2P). Current P2P provided by NVIDIA CUDA dri
 ver is limited ...\n\n\nI-Hsin Chung (IBM) and Yomi Yeh, Andy Yang, and Br
 ian Pan (H3 Platform Inc)\n---------------------\nNVXL Acceleration Platfo
 rm for Polymorphic Acceleration\n\nNVXL has engineered a scalable approach
  to address the ever-increasing need for compute performance using a new t
 echnology: polymorphic acceleration. Polymorphic acceleration is the only 
 technology that is built on the general premise that a multitude of comput
 e-intensive applications needs a multit...\n\n\nJeffery Bunting, Samit Cha
 udhuri, and Michael Chang (NVXL Technology Inc)\n---------------------\nPa
 rallelware Analyzer: Speeding Up the Parallel Software Development Lifecyc
 le.\n\nParallelware Analyzer is the second product in the Parallelware Too
 ls Suite and is being designed around the needs of the user.  Parallelware
  Analyzer is a command line reporting tool designed to help the HPC applic
 ation developer speed up their development process, and also provide the H
 PC service ...\n\n\nToni Collis (Appentra Solutions, Collis-Holmes Innovat
 ions Limited) and Manuel Arenaz, Javier Novo Rodríguez, Daniel Otero Oubiñ
 a, Jaime González Cuevas, and Belén Torrente Torrente (Appentra Solutions)
 \n---------------------\nDAQDB - a Distributed Key-Value Store for Petasca
 le Hot Storage\n\nHigh-capacity persistent memory, fast SSD-based storage,
  and platform-integrated RDMA network transport open new opportunities in 
 the design of high-bandwidth data acquisition systems. Petascale hot stora
 ge solutions for data incoming at rate of multi TB/s over long periods of 
 time are now becoming ...\n\n\nGrzegorz Jereczek, Maciej Maciejewski, Piot
 r Pelplinski, Jakub Radtke, Pawel Makowski, and Aleksandra Wisz (Intel Cor
 poration)\n\nRegistration Category: Tech Program Reg Pass, Exhibits Reg Pa
 ss, Exhibits - Exhibit Hall Only Reg Pass
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