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Workshop
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MCHPC’18: Workshop on Memory Centric High Performance Computing
Event Type
Workshop
Tags
Memory
NVRAM
Parallel Programming Languages, Libraries, and Models
Registration Categories
W
TimeSunday, November 11th9:00am - 5:30pm CST
LocationD170
Presentations
9:00am - 9:02am CSTIntroduction - MCHPC’18: Workshop on Memory Centric High Performance Computing
9:02am - 10:00am CSTMCHPC'18 Morning Keynote: Converging Storage and Memory
Presenter
10:00am - 10:30am CSTWorkshop Morning Break
10:30am - 10:52am CSTChallenges of High-Capacity DRAM Stacks and Potential Directions
10:52am - 11:14am CSTEvaluation of Intel Memory Drive Technology Performance for Scientific Applications
11:14am - 11:30am CSTxBGAS: Toward a RISC-V ISA Extension for Global, Scalable, Shared Memory
11:30am - 11:52am CSTUnderstanding Application Recomputability without Crash Consistency in Non-Volatile Memory
Author/Presenters
11:52am - 12:14pm CSTA Preliminary Study of Compiler Transformations for Graph Applications on the Emu System
12:14pm - 12:30pm CSTData Placement Optimization in GPU Memory Hierarchy Using Predictive Modeling
12:30pm - 2:00pm CSTWorkshop Lunch (on your own)
2:00pm - 3:00pm CSTMCHPC'18 Afternoon Keynote: All Tomorrow’s Memory Systems
Presenter
3:00pm - 3:30pm CSTWorkshop Afternoon Break
3:30pm - 3:52pm CSTOn the Applicability of PEBS-Based Online Memory Access Tracking for Heterogeneous Memory Management at Scale
3:52pm - 4:14pm CSTExploring Allocation Policies in Disaggregated Non-Volatile Memories
4:14pm - 4:30pm CSTHeterogeneous Memory and Arena-Based Heap Allocation
4:30pm - 5:30pm CSTMCHPC'18 Panel: Research Challenges in Memory-Centric Computing
Presenter
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